It has been proposed to alter the body biasing voltages of transistors of an integrated circuits in order to increase performance and/or reduce power consumption.
A shift towards SOI (silicon on insulator) based transistor technology makes body biasing a particularly interesting proposition as this technology permits a relatively broad range of biasing voltages, for example from as low as −3 V to as high as +3 V, to be applied to the body of the devices. This compares to a more limited body biasing range of −300 mV to +300 mV in the case of bulk transistors. The biasing voltage is applied to the p-type or n-type well underlying each SOI transistor device, sometimes referred to as the back gate.
For example, forward body biasing (FBB) involves applying a body biasing voltage to decrease the transistor threshold voltage and thus increase performance by increasing the speed of the transistors. Reverse body biasing (RBB) involves applying a body biasing voltage that increases the transistor threshold voltage and thus reduces current leakage and power consumption.
Existing techniques for generating forward and reverse body biasing voltages have drawbacks in terms of complexity and/or lead to relatively poor power consumption for a given performance level.